Lidded integrated circuit package

ABSTRACT

A lid comprising a heat conductive substrate and a native silicon oxide layer connected to said substrate by at least one intermediate layer; a lidded integrated circuit package; and a method of providing a heat path through an integrated circuit package comprising providing a substrate with an exterior layer of native silicon oxide and interfacing the layer of native silicon oxide with a layer of thermal interface material.

BACKGROUND

Lidded integrated circuit packages (“lidded IC packages”) are often usedwith semiconductor dies and/or printed circuit boards (“PC boards”) thatgenerate significant amounts of heat. A typical lidded IC packageincludes a semiconductor die mounted on an electrical connectionsubstrate. A lid, made from a conductive material is mounted on thesubstrate on the same side as the die. The lid completely encloses thesemiconductor die, which is positioned beneath it. A thermal interfacematerial such as silicone or epoxy is positioned between the die and thelid. The thermal interface material facilitates heat flow between thesemiconductor die and the lid. A heat sink is typically mounted on theupper surface of the lid to receive and disperse heat from the lid.

Currently most lids are made of nickel coated copper. The nickel layeris, in turn, coated with a silicon oxide material applied by physicalvapor deposition. Physical vapor deposition typically uses evaporationor sputtering techniques to apply a silicon dioxide coating bycondensation of vapors in a vacuum resulting in adhesion between thedeposited atoms and atoms of the nickel layer. The silicon oxide layerof the lid interfaces with the thermal interface material that isapplied to it.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top plan view of a lid for a lidded IC package.

FIG. 2 is a cross-sectional view of the lid of FIG. 1.

FIG. 3 is a bottom plan view of the lid of FIG. 1.

FIG. 4 is an exploded perspective view of the principal components of alidded IC package.

FIG. 5 is a cross-sectional view of a lidded IC package having a heatsink mounted thereon.

FIG. 6 is a detail, cut away, cross-sectional view of a central bodyportion of the lid illustrated in FIGS. 1-3 mounted on a die, asillustrated in FIG. 5.

FIG. 7 is a flow diagram of a method of providing a heat path through anintegrated circuit package.

DETAILED DESCRIPTION

In this disclosure terms such as up, down, top, bottom, vertical,lateral and the like are used in a relative sense to describe thepositional relationship of various components of a lidded IC package 10and adjacent structure. These terms are used with reference to theposition of components shown in the drawing, not in an absolute sensewith reference to a field of gravity. Thus, for example, a surface shownin the drawing and referred to as the top surface 72 of die 70 wouldstill be properly referred to as the top surface of the die, even if, ina real world situation, the die were placed in an inverted position withrespect to the position shown and described in this disclosure.

This description, in general, discloses a lidded integrated circuit (IC)package 10 that has a lid 20 with a heat conductive substrate 21 and anative silicon oxide layer 54 connected to said substrate 21 by at leastone intermediate layer, 40, 50. These intermediate layers may include anickel layer 40 coated on the substrate 21 and a crystallized amorphoussilicon film layer 50 interfacing with the nickel layer 40. The nativesilicon oxide layer 54 may be formed on the crystallized amorphoussilicon film layer 50. The heat conductive substrate 21 may be a coppersubstrate. The substrate 21 may have a generally rectangular centralbody 22 and a peripheral flange 28 extending from the central bodyportion 22.

The lidded IC package 10 may include a semiconductor die 70 mounted onan electrical connection substrate 80. The flange 28 of the lid 20 maybe mounted on the electrical connection substrate 80 such that thecentral body 22 of the lid is positioned over the die 70. A layer ofthermal interface material 60 is attached to the top surface of thesemiconductor die 70 and to the native silicon oxide layer 54 of thelid. The layer of thermal interface material 60 may be silicone or epoxyresin with thermally conductive filler media.

Having thus described the structure of a lidded IC package generally,the lidded IC package and way it is produced will now be described ingreater detail.

FIG. 5 is a cross sectional view of the entire lidded IC package 10 witha heat sink 12 mounted on top of it. FIGS. 1-4 show that the lid 20 hasan inverted, open, box shape. The lid 20 includes a generallyrectangular central body 22 having a top surface 24 and a bottom surface26. The lid further includes a peripheral flange 28 extending from thecentral body 22. The peripheral flange 28 has a generally verticallydisposed leg portion 30 and a laterally outwardly extending foot portion32 with a bottom surface 33. Although the embodiment of the lid shown inthe drawings is a “top hat” type lid, other types of lids such as “flatlids” and “cavity lids” may also be used. FIG. 4 shows that the die 70and substrate 80 both have a generally box shaped appearance. FIG. 4further shows the general positional relationship of the lid 20,semiconductor die 70 and electrical connection substrate 80. The die 70is mounted above the electrical connection substrate 80. The lid 20 ismounted above both the substrate 80 and the die 70. The lid 20 andsubstrate 80 enclose the die 70 on all sides, top and bottom.

Referring to FIG. 5, the heat sink 12 shown is a fin type, air-cooledheat sink, but any other type of heat sink including a liquid cooledheat sink might be used as well, depending upon the particularapplication. The heat sink 12 has a bottom surface 14 which interfaceswith a layer of thermal interface material 16 having a top surface 17and a bottom surface 18. Various types of thermal interface material maybe used such as thermal grease, thermal gel, or graphite sheet interfacematerial, all of which are known in the art. The methods of applying andusing such thermal interface material are also well known in the art andwill thus not be further described herein. The thermal interfacematerial 16 is applied to a top portion of a lid 20.

FIG. 6 is a detailed cross sectional view of a central portion of thelid 20 as well as other components. The lid 20 may be divided into amain, heat conductive copper substrate portion 21 and a layered portion19 that is applied to the main portion. As previously described thecopper substrate portion 21 includes a copper central body 22 and aperipheral copper flange 28 which is integrally formed with the centralbody 22. The layered portion 19 of the lid 20 interfaces with and ispositioned below the central body portion 22 of the copper substrate 21.The copper substrate may typically be about 1 mm to 2 mm thick. Thelayered portion 19 may typically be about 0.025 um (microns) to 7 umthick. As best illustrated by FIG. 6, the layered portion 19 includes anickel film layer 40, which is formed on the bottom surface 25 of thecopper substrate 21. An upper surface 42 of the nickel film layer thusinterfaces with the bottom surface 25 of the copper substrate 21. Thenickel layer may have a typical thickness of about 0.25 to 6 um. Thenickel film layer 40 may be deposited on the bottom surface 25 of thecopper substrate 21 by various methods well known in the art includingelectrolytic deposition and electroless deposition.

A layer of amorphous silicon (a-Si) is deposited on the lower surface 44of the nickel film layer as by low pressure chemical vapor deposition(LPCVD) or chemical vapor deposition (CVD). Such deposition techniquesare well known in the art, see for example U.S. Pat. No. 4,894,352 ofLane et al., issued Jan. 16, 1990 and entitled DEPOSITION OFSILICON-CONTAINING FILMS USING ORGANOSILICON COMPOUNDS AND NITROGENTRIFLUORIDE, which is hereby incorporated by reference for all that isdisclosed therein. After being deposited, the a-Si film is transformedinto polycrystalline silicon by a metal induced crystallizationmechanism produced by the presence of nickel which reacts with thesilicon. This crystallization transformation process takes placespontaneously over time under ambient conditions, and typically takesseveral hours. Thus, a layer of polycrystalline silicon 50 having anupper surface 52 interfacing with the nickel film layer 40 is provided.

Polycrystalline silicon when exposed to air under ambient conditionsspontaneously grows native silicon oxide. At ambient conditions a layerof native silicon oxide about 3 molecules thick (less than 1 nanometer)will typically grow in a few hours. The speed of this process may beincreased somewhat by an elevated temperature e.g., about 500° C., atambient pressure for a period of about 90 minutes. See Nickel InducedCrystallization of Amorphous Silicon Thin Films by Zhonghe Jin, GururajA. Bhat, Milton Yeung, Hoi S. Kwok, and Man Wong of the Department ofElectrical and Electronic Engineering, Hong Kong University of Scienceand Technology, Clear Water Bay, Kowloon, Hong Kong, JOURNAL OF APPLIEDPHYSICS, VOUME 84, NUMBER 1 and also Growth of Native Oxide on a SiliconSurface by M. Morita, T. Ohmi, E. Hasegawa, M. Kawakami, and M. Ohwadaof Department of Electonics Faculty of Engineering, Tohoku University,Sendai 980, Japan, JOURNAL OF APPLIED PHYSICS, VOUME 68 NUMBER 3, whichare both hereby incorporated by reference for all that is disclosedtherein. Thus, a layer of native silicon oxide 54 may be provided at thelower portion of the polycrystalline silicon layer 50 simply throughexposure of the polycrystalline silicon layer to air. Whether the nativesilicon oxide growth takes place at normal room temperature or atelevated temperature, there is typically a maximum growth amount whichwill take place. Growth sufficient to produce a three molecule thicklayer of native silicon oxide 54 is sufficient. The lower surface 56 ofthe native silicon oxide layer 54 forms the bottom of the layeredportion 19 and is thus the bottom surface 26 of the lid 20. After theformation of the layered portion 19 of the lid 20 has been completed thelid 20 may be mounted on the substrate 80, as described below.

Having thus described the structure of lid 20 and the manner by whichlid 20 is produced, the remaining structure of the lidded IC package 10,as shown in FIGS. 5 and 6 will now be briefly described. The manner inwhich this structure is assembled will be described in detail laterherein.

A layer of thermal interface material 60, which may be a silicone orepoxy resin filled with thermally conductive media, interfaces with thebottom surface 56 of the native silicon oxide layer 54 which is also thebottom surface 26 of the lid 20. The layer of thermal interface material60 thus has a top surface 62 interfacing with the bottom surface 26 ofthe lid 20 and a bottom surface 64 interfacing with a top surface 72 ofthe silicon die 70. The layer of thermal interface material may have atypical thickness of about 10-100 um. (The surface referred to as thetop surface 72 of the die in this specification is also frequentlyreferred to as the “back side” of the die in the art. The phrase “topsurface” will be used herein to provide an easily understood frame ofreference when referring to certain other structure. Similarly thephrase “bottom surface 74” will be used in this specification whenreferring to the die surface positioned opposite to the “top surface 72”even though the phrase “front side” of the die is often used in the artwhen referring to this surface.)

As illustrated best by FIG. 5, die 70 may be a flip chip type of dieinterconnect for a lidded package which is physically and electricallyconnected to an electrical connection substrate 80. However, it will beunderstood by those skilled in the art that any other type of dieinterconnect for a lidded package could also be used. The substrate 80has a top surface 82 with electrical contacts 83, etc., FIG. 4. Theelectrical contacts 83, etc., on the electrical connection substrate 80may be connected to electrical contacts, such as solder bumps 75, on thedie 70. The electrical connection substrate 80 also has a bottom surfacewith a structure such as, for example, a ball grid array 86 that allowsthe substrate 80 to be physically and electrically connected to a PCboard 90.

Having thus described the structure and manner of making lid 20 and theoverall structure of lidded IC package 10, the method by which liddedpackage 10 is assembled will now be described.

The first sequence of operations, known as die attach, involvessoldering semiconductor die 70 to the electrical connection substrate80, which may be an organic substrate or another type of substrate. Thisoperation physically and electrically attaches die 70 to substrate 80.Initially solder paste is applied to the top surface 82 of substrate 80in the region where die 70 is to be mounted. Next, die 70 is picked upand placed in proper orientation on substrate 80 by a pick and placemachine. The layer of solder paste is sandwiched between the bottomsurface 74 of die 70 and the top surface 82 of substrate 80. The solderpaste is sufficiently tacky to hold die 70 in place during displacementof the die/substrate assembly. Next the die/substrate assembly is movedto a reflow oven (not shown) where it is heated to a predeterminedtemperature and then maintained at that temperature for a preset periodof time. During this heating period the solder paste melts and forms ametallurgical bond with die 70 and substrate 80 once the soldersolidifies. This bonding strengthens as the solder cools. Reflow heatingof dies and substrates is well understood by those skilled in the art.The reflow oven temperature and heating period will vary depending uponparticular die/substrate and/or environmental parameters and may bedetermined empirically for any particular set of parameters or may bebased upon production algorithms and guidelines developed by thefabrication facility. The die 70 is thus rigidly attached to thesubstrate 80 by a solder layer 76. The die 70 may have solder bumps 75or other electrical interconnect structure on bottom surface 74, whichare adapted to electrically connect the die 70 to bonding pads 83, etc.,or the like on the top surface 82 of substrate 80, FIG. 4. Solder pasteat 75 melts and bonds to the bonding pads 83, etc., during reflowheating forming solder bumps. The regions beneath the die 70 that arenot filled with solder are then packed with a material known asunderfill, which relieves stresses that may develop in the solderattached portions of the die and substrate due to heating and coolingcycles, etc. The underfill is then cured in an oven for a set time andduration particular to the material to fully crosslink the underfill andstabilize its viscosity. The mounting and solder attachment ofsemiconductor dies to substrates with solder, solder bumps and underfillare well known in the art.

The next process performed is called lid attach. The structure of thelid 20 and the method by which it is made are described above. Thisprocess of lid formation is completed prior to lid attach. During lidattach, lid adhesive 34 is placed about the periphery of the top surface82 of substrate 80. At approximately the same time a thermal interfacematerial 60, which may be silicone or epoxy resin with thermallyconductive filler media, is applied in paste form to the top surface 72of die 70. The thermal interface material may be applied by differentmethods known in the art. In one embodiment the thermal interfacematerial 60 is applied in a predetermined pattern from a syringe in anelectronically controlled dispense apparatus. A pick and place machineis then used to place lid 20 on substrate 80. The lid 20 is positionedsuch that the lower surface 33 of flange foot portion 32 engages theperipheral strip of lid adhesive 34. The depth of the lid 20 and theheight of the thermal interface material paste 60 above the die topsurface 72 is such that the bottom surface 26 of the lid engages theupper surface 62 of the paste 60 as the lid 20 is mounted on thesubstrate 80. Downward pressure from the lid 20 causes the paste 60 tospread across the die top surface 72 as the lid 20 is urged downwardlyonto substrate 80. Thereafter, a predetermined downward force ismaintained on the lid 20 for a predetermined period of time, and at apredetermined temperature, during which the lid adhesive 34 and thethermal material 60 is cured. The time, pressure and temperature may bedetermined empirically or may be determined analytically from knownalgorithms and guidelines used at the particular fabrication facility.During the curing process the thermal interface material 60 forms highstrength bonds with the native silicon oxide layer 54 of the lid 20reducing the chance that the thermal interface material will tear awayfrom the lid during subsequent heating and cooling cycles, etc. By thusreducing delamination, heat transfer efficiency between the lid and thethermal interface material is improved. The native silicon oxide layeris atomically flat (<0.1 nm) which further enhances heat transfer byproviding more points of contact over the lid surface thanconventionally formed silicon oxide layers. The thin native oxide layeralso provides more efficient heat transfer than conventional thermaloxide layers, which are much thicker. The native silicon oxide layer isalso highly resistant to moisture ingress. Thus a lid/thermal interfacematerial attachment is provided that has improved shear strength anddelamination resistance and improved moisture resistance withoutresorting to the use of high modulus thermal interface materials and/orthicker thermal oxide layers with their resulting heat transferinefficiencies.

As further illustrated by FIG. 5, heat sink 12 may be installed on topof lid 20. Although this operation may be performed by the liddedpackage manufacturer, it is more typically performed at the facility ofa customer of the manufacturer. The heat sink 12 may be secured to thelid 20 with a thermal interface material 16 such as silicone or epoxyresin with thermally conductive filler media that is applied to the lid.The heat sink 12 is then placed on the lid 20 in a desired orientationby use of a pick and place machine.

The mounting of a heat sink 12 on lid 20 may take place before or afterthe mounting of the lidded package 10 on a PC board 90, which is shownin dashed lines in FIG. 5. In the embodiment illustrated in FIG. 5, theelectrical connection substrate 80 has a ball grid array which isconnected to corresponding connection structure (not shown) on the PCboard 90. In this embodiment the lidded IC package 10 is placed in theappropriate orientation on the PC board 90 by a pick and place machine.The entire assembly is then moved to a reflow oven and heated until thesolder balls of the ball grid array 86 melt and metallurgically bondwith contacts on the PC board upon solidification. The method ofattachment of ball grid array electrical connection substrates, as wellas various other types of electrical connection substrates, to PC boardsis well known is the art.

FIG. 7 discloses a method of providing a heat path through an integratedcircuit package. The method includes, as shown at 122 providing asubstrate with an exterior layer of native silicon oxide. The methodfurther includes, as shown at 124, interfacing the layer of nativesilicon oxide with a layer of thermal interface material.

While certain illustrative embodiments of an integrated circuit packageand associated methodology have been described in detail herein, it willbe obvious to those with ordinary skill in the art after reading thisdisclosure that the disclosed integrated circuit package and methodologymay be variously otherwise embodied and employed. For example, eventhough a method for forming a bottom portion of a lid is specificallydescribed, it will be understood by those skilled in the art who haveread this disclosure that this same methodology could be employed forforming a top portion of a lid if desired. The appended claims areintended to be broadly construed to include variations which are notexcluded by claim language or the prior art.

What is claimed is:
 1. A lidded integrated circuit (IC) packagecomprising a lid having a heat conductive substrate and a native siliconoxide layer connected to said substrate by at least one intermediatelayer.
 2. The lidded integrated circuit (IC) package of claim 1 whereinsaid lid further comprises a nickel layer disposed between saidsubstrate and said native silicon oxide layer.
 3. The lidded integratedcircuit (IC) package of claim 1 wherein said lid further comprises acrystallized amorphous silicon film layer disposed between saidsubstrate and said native silicon oxide layer.
 4. The lidded integratedcircuit (IC) package of claim 1 wherein said heat conductive substratecomprises a copper substrate.
 5. The lidded integrated circuit (IC)package of claim 4 wherein said lid further comprises a nickel layerdeposited on said copper substrate.
 6. The lidded integrated circuit(IC) package of claim 5 wherein said lid further comprises acrystallized amorphous silicon layer deposited on said nickel layer. 7.The lidded integrated circuit (IC) package of claim 6 wherein saidnative silicon oxide layer is formed on said crystallized amorphoussilicon layer.
 8. The lidded integrated circuit (IC) package of claim 1further comprising: a semiconductor die having a top surface and abottom surface; and a layer of thermal interface material attached tosaid top surface of said semiconductor die and to said native siliconoxide layer of said lid.
 9. The lidded integrated circuit (IC) packageof claim 8 wherein said lid comprises a central body portion whichcomprises said native silicon oxide layer, and a peripheral flangeportion and further comprising an electrical connection substrate,wherein said peripheral flange is connected to said electricalconnection substrate.
 10. The lidded integrated circuit (IC) package ofclaim 8 wherein said semiconductor die is mounted on said electricalconnection substrate.
 11. The lidded integrated circuit (IC) package ofclaim 8 wherein said thermal interface material comprises at least oneof silicone and epoxy.
 12. The lidded integrated circuit (IC) package ofclaim 1 wherein said lid comprises a central body portion and aperipheral flange portion and further comprising: a semiconductor diehaving a top surface and a bottom surface; a layer of thermal interfacematerial attached to said top surface of said semiconductor die and tosaid native silicon oxide layer of said lid; and an electricalconnection substrate, wherein said peripheral flange of said lid isconnected to said electrical connection substrate.
 13. The liddedintegrated circuit (IC) package of claim 12: wherein said liddedintegrated circuit package is mounted on a PC board operativelyconnected to said electrical connection substrate; and wherein saidlidded integrated circuit package has a heatsink mounted thereon whichis operatively connected to said lid.
 14. A lid comprising a heatconductive substrate and a native silicon oxide layer connected to saidsubstrate by at least one intermediate layer.
 15. The lid of claim 14wherein said heat conductive substrate comprises a copper substrate. 16.The lid of claim 15 wherein said lid further comprises a nickel layerdeposited on said copper substrate.
 17. The lid of claim 16 wherein saidlid further comprises a crystallized amorphous silicon layer depositedon said nickel layer.
 18. The lid of claim 17 wherein said nativesilicon oxide layer is formed on said crystallized amorphous siliconlayer.
 19. A method of providing a heat path through an integratedcircuit package comprising: providing a substrate with an exterior layerof native silicon oxide and interfacing the layer of native siliconoxide with a layer of thermal interface material.
 20. The method ofclaim 19 wherein interfacing the layer of native silicon oxide with alayer of thermal interface material comprises at least one ofinterfacing the layer of native silicon oxide with a layer of siliconeand interfacing the layer of native silicon oxide with a layer of epoxy.